INCH-POUND
The documentation and process conversion
measures necessary to comply with this
MIL-PRF-19500/349J
revision shall be completed by 25 July 2011.
10 June 2011
SUPERSEDING
MIL-PRF-19500/349H
25 August 2009
PERFORMANCE SPECIFICATION SHEET
SEMICONDUCTOR DEVICE, TRANSISTOR, NPN, SILICON, SWITCHING,
TYPES 2N3506, 2N3506A, 2N3506L, 2N3506AL, 2N3506U4, 2N3506AU4, 2N3507, 2N3507L,
2N3507A, 2N3507AL, 2N3507U4, AND 2N3507AU4, JAN, JANTX, JANTXV, JANS, JANSM, JANSD,
JANSP, JANSL, JANSR, JANSF, JANSG, JANSH, JANHCA, JANKCA, JANKCAM,
JANKCAD, JANKCAP, JANKCAL, JANKCAR, JANKCAF, JANKCAG, and JANKCAH
This specification is approved for use by all Departments
and Agencies of the Department of Defense.
The requirements for acquiring the product described herein shall consist of
this specification sheet and MIL-PRF-19500.
1. SCOPE
1.1 Scope. This specification covers the performance requirements for NPN, silicon, switching transistors. Four
levels of product assurance are provided for each device type as specified in MIL-PRF-19500. Two levels of product
assurance are provided for each unencapsulated device type. Provisions for radiation hardness assurance (RHA) to
eight radiation levels is provided for JANTXV, JANS, JANHC, and JANKC product assurance levels. RHA level
designators "M", "D", "P", "L", "R", "F", "G", and "H" are appended to the device prefix to identify devices, which have
passed RHA requirements.
1.2 Physical dimensions. See figure 1 (similar to TO-39) and figure 2 (U4), and figure 3 for JANHC and JANKC
(die) dimensions.
1.3 Maximum ratings unless otherwise specified TA = +25°C. (1)
Types
PT
PT
RθJA
RθJC
VCBO
VCEO
VEBO
IC
TJ and
TA = +25°C
TC = +25°C
(2)
(2)
TSTG
(1)
(1)
°C/W
°C/W
°C
V dc
W
W
V dc
V dc
A dc
2N3506, 2N3506A,
1.0
5.0
60
40
5.0
3.0
175
18
2N3506L, 2N3506AL
1.0
5.0
175
18
60
40
5.0
3.0
2N3506U4
1.0
5.0
175
7
60
40
5.0
3.0
-65 to
2N3507, 2N3507A,
1.0
5.0
175
18
80
50
5.0
3.0
+200
2N3507L, 2N3507AL
1.0
5.0
175
18
80
50
5.0
3.0
2N3507U4
1.0
5.0
175
7
80
50
5.0
3.0
(1) For derating see figures 4, 5, and 6.
(2) For thermal impedance see figures 7, 8, and 9.
* Comments, suggestions, or questions on this document should be addressed to DLA Land and Maritime, ATTN:
VAC, P.O. Box 3990, Columbus, OH 43218-3990, or emailed to Semiconductor@dla.mil. Since contact information
can change, you may want to verify the currency of this address information using the ASSIST Online database at
AMSC N/A
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