MIL-PRF-19500 Semiconductor Devices, General Specification ForThis specification establishes the general performance requirements for semiconductor devices. Product assurance is provided by effective screening, conformance inspection, and process controls to mitigate risk. Mission assurance and standardization of parts are the highest priorities. This specification establishes a heritage program of semiconductor devices the military and space community can rely on to be dependable and available. Detail requirements and characteristics are specified in the specification sheets. Revisions to this specification and specification sheets are structured to assure the interchangeability of devices of the same part type regardless of manufacturing date code or conformance inspection \(CI\) completion date. Four quality levels for encapsulated devices are provided for in this specification, differentiated by the prefixes JAN, JANTX, JANTXV, and JANS. Eight radiation hardness assurance \(RHA\) levels are provided for the JANTXV and JANS quality levels. These are designated by the letters M, D, P, L, R, F, G, and H following the quality level portion of the prefix. Two quality levels for unencapsulated devices are provided for in this specification, differentiated by the prefixes JANHC and JANKC.

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MIL-PRF-19500P

APPENDIX G

DISCRETE SEMICONDUCTOR DIE/CHIP LOT ACCEPTANCE

G.1 SCOPE

G.1.1 Scope. The purpose of this appendix is to establish minimum standards for screening and qualification of

JANHC and JANKC unencapsulated discrete semiconductor devices (die/chips) for use in semiconductor devices.

This appendix is a mandatory part of the specification. The information contained herein is intended for compliance.

G.2 APPLICABLE DOCUMENTS. This section is not applicable to this appendix.

G.3 DEFINITIONS

G.3.1 Date code. Seal week of the element evaluation (EE) packaged samples.

G.3.2 Die/chips. Unencapsulated discrete semiconductors. The term chip is interchangeable with the term die.

G.3.3 Manufacturer. Original wafer lot fabricator.

G.3.4 Identification. See 1.3 for identification.

G.3.5 Wafer lot. A wafer lot shall consist of only semiconductor wafers subjected to each and every process step

as a group. Each wafer lot shall be assigned a unique identifier which provides traceability to all wafer processing

steps. Rework provisions shall be in accordance with D.3.13.2. Wafer lot records shall identify all JANHC and

JANKC device inspection lots formed from the wafer lot.

G.3.6 Inspection lot. An inspection lot shall consist of one device type from a single wafer lot.

G.4 REQUIREMENTS

G.4.1 General. Semiconductor die shall conform to the requirements contained herein.

G.4.2 Steady-state life and screening. Steady-state life time and temperatures shall be in accordance with table

G-I. Semiconductor die shall be screened in accordance with table G-II, subgroups 1 and 2 (see G.5.2.1 and

G.5.2.2).

G.4.3 Qualification. Qualification shall be based on the results of the first EE performed and submitted to DLA

Land and Maritime.

G.4.3.1 Wafer fabrication. Qualification shall be performed by the basic plant or original wafer lot manufacturer

from die manufactured in the same wafer fab that was used to qualify a PIN on the QML of the same function and

technology. Qualification for JANKC can only be approved on die processed in a wafer fab that has been used to

qualify a JANS part on the QML of the same technology and function. For the purpose of this specification, examples

of function are: Signal transistor, fast recovery epitaxial diode (FRED), power transistor, zener diode, rectifier or

transient suppressor. The term technology may include: Diffusion metal oxide semiconductor (DMOS), V-groove

metal oxide semiconductor (VMOS), diffused junction, alloy junction, junction field effect transistor (JFET) and

Schottky.

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