MIL-PRF-19500 Semiconductor Devices, General Specification ForThis specification establishes the general performance requirements for semiconductor devices. Product assurance is provided by effective screening, conformance inspection, and process controls to mitigate risk. Mission assurance and standardization of parts are the highest priorities. This specification establishes a heritage program of semiconductor devices the military and space community can rely on to be dependable and available. Detail requirements and characteristics are specified in the specification sheets. Revisions to this specification and specification sheets are structured to assure the interchangeability of devices of the same part type regardless of manufacturing date code or conformance inspection \(CI\) completion date. Four quality levels for encapsulated devices are provided for in this specification, differentiated by the prefixes JAN, JANTX, JANTXV, and JANS. Eight radiation hardness assurance \(RHA\) levels are provided for the JANTXV and JANS quality levels. These are designated by the letters M, D, P, L, R, F, G, and H following the quality level portion of the prefix. Two quality levels for unencapsulated devices are provided for in this specification, differentiated by the prefixes JANHC and JANKC.

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MIL-PRF-19500P

Distributor documentation for each distributor:

(1) Distributor's name and address.

(2) Name and address of customer.

(3) Quantity of devices in shipment.

(4) Certification that this shipment is a part of the shipment covered by the manufacturer's

documentation, and an attached copy of the manufacturer's original certification.

(5) Signature and date of transaction.

(6) Certification that authorized dealers and distributors have handled the products in accordance with

the requirements of JEDEC Standard JESD-31 and JESD-625.

(7) Device type, quality level, and lot identification code.

(8) Manufacturer's name.

3.8 Critical interface and materials. Critical interface and materials for devices furnished under this specification

shall be such that the devices meet the performance requirements of 3.3 (see appendix H).

3.9 Lead and terminal finish. The lead and terminal finish shall be in accordance with appendix H herein.

3.10 Marking.

3.10.1 Marking on each device. The following marking shall be placed on each encapsulated semiconductor

device and shall be legible. Devices having inadequate marking area for all applicable markings shall have as many

of the following as possible, in the following order of precedence (with "a." being most important). Unencapsulated

semiconductor devices (die) do not require individual device marking. JAN marking shall be performed by the basic

plant. Marking may be performed in any wholly owned certified facility with the approval of the qualifying activity.

Marking shall not be performed by any contracted facility.

Polarity marking, when applicable (see 3.10.5).

PIN (see 3.10.6).

Manufacturer's name, trademark, or identification (see 3.10.12) or manufacturer's designating symbol (see

3.10.7).

Lot identification code and code for plants (see 3.10.8 and 3.10.8.2).

Serial number, if applicable (see 3.10.9).

DMS marking, if applicable (See 3.10.10).

Special marking (see 3.10.3). Beryllium oxide identifier (see 3.10.3.2). The "P" suffix marking for PIND

testing (see 1.3.7) may follow the type number or be marked any place on the device within the marking

area.

Electrostatic discharge sensitivity (ESDS) identifier (optional see 3.10.3.1).

Country of origin (optional see 3.10.11).