MIL-PRF-19500P
APPENDIX E
E.3 GENERAL TEST AND INSPECTION INFORMATION
E.3.1 Wafer lots. Wafer lots consist of semiconductor wafers formed into lots at the start of wafer fabrication for
processing as a group. Each lot is assigned a unique identifier to provide traceability and maintain lot integrity
throughout the fabrication process. The wafer lot shall be traceable to the silicon lot(s) or portion thereof. The
maximum number of wafers in the wafer lot size shall be defined by the manufacturer. Wafer lot processing as a
group is accomplished by any of the following procedures, providing process schedules and controls are sufficiently
maintained to assure identical processing in accordance with process instructions of all wafers in the lot:
a.
Batch processing of all wafers in the wafer lot through the same machine process steps simultaneously.
b.
Continuous and sequential processing (wafer by wafer or batch portions of wafer lot) of all wafers through
the same machine(s) or process steps. No other product, lots, equipment maintenance, repair, or
calibration shall interrupt continuous or sequential processing. Any deviation from this processing requires
the written approval of the qualifying activity or a new wafer lot identifier will be assigned.
E.3.1.1 Formation of inspection lots. JAN, JANTX, and JANTXV devices shall be assembled into an identifiable
inspection lot or collection of inspection sublots. JANS devices shall be assembled into an identifiable inspection lot.
Each inspection lot shall be identified by a unique lot identification code (see 3.10.8).
E.3.1.1.1 JAN, JANTX, and JANTXV inspection lot. The total number of devices that the manufacturer submits at
any one time for qualification or conformance inspection and which conforms to the following criteria shall constitute
an inspection lot.
a. The maximum small inspection lot size shall be 2,500 devices.
b. The lot accumulation period shall not exceed 6 consecutive calendar weeks of device seal operations. The
inspection lot is submitted to determine compliance with the requirements of the specification sheets.
c. Each inspection lot shall consist of devices of a single device type or consist of a collection of sublots of
structurally identical device types contained on one or more specifications sheets (see E.3.1.1.1.1 and E.3.2).
d. Assembly lot identification shall be maintained from the time the lot is kitted.
e. The entire inspection lot shall be accumulated prior to initiating conformance inspection. Samples shall be
randomly selected from the entire inspection lot.
E.3.1.1.1.1 Inspection sublot. An inspection sublot shall be a single device type (part number) contained on a
single specification sheet manufactured on the same production line(s) through final seal and to the same device
design with the same material requirements and within the same 6-week lot accumulation period.
E.3.1.2 JANS lots.
E.3.1.2.1 Scanning electron microscope (SEM) inspection. If any wafer lot is of a selected die design (such as
overlay structure devices and devices with metallization path to bond pad crossing any junction covered by
passivation or glassivation where the bonding pad is not on the same active area of the device), SEM inspection is
required prior to acceptance of the wafer lot (generally this is applicable only on particular small signal bipolar
transistors and MOSFETs). This inspection shall be performed in accordance with, test method 2077 of MIL-STD-
750, for each of these lots. If a contracted laboratory is used for the actual SEM inspection, the manufacturer shall
document and define the responsibilities of the manufacturer and contractor regarding steps within test method 2077
that may be performed by either party, such as: Sample selection and sample preparation.
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