MIL-PRF-19500/287G
*
4.3.1 Power burn-in conditions. Power burn-in conditions are as follows: VCB = 10 - 30 V dc. Power shall be
applied to achieve TJ = +135°C minimum using a minimum PD = 75 percent of PT maximum rated as defined in
1.3. With approval of the qualifying activity and preparing activity, alternate burn-in criteria (hours, bias conditions,
TJ, and mounting conditions) may be used for JANTX quality levels. A justification demonstrating equivalence is
required. In addition, the manufacturing site's burn-in data and performance history will be essential criteria for
burn-in modification approval.
* 4.3.2 Thermal impedance. The thermal impedance measurements shall be performed in accordance with
method 3131 of MIL-STD-750 using the guidelines in that method for determining IM, IH, tH, tSW (VC and VH
where appropriate). Measurement delay time (tMD) = 70 μs max. See table III, group E, subgroup 4 herein.
* 4.4 Conformance inspection. Conformance inspection shall be in accordance with MIL-PRF-19500 and as
specified herein. If alternate screening is being performed in accordance with MIL-PRF-19500, a sample of
screened devices shall be submitted to and pass the requirements of subgroup 1 and 2, of table I herein,
inspection only (table E-VIb, group B, subgroup 1 is not required to be performed since solderability and
resistance to solvents testing is performed in table I herein.
4.4.1 Group A inspection. Group A inspection shall be conducted in accordance with MIL-PRF-19500 and
table I herein.
4.4.2 Group B inspection. Group B inspection shall be conducted in accordance with the tests and conditions
specified in 4.4.2.1 for JAN and JANTX group B testing. Electrical measurements (end-points) and delta
requirements for JAN and JANTX shall be after each step in 4.4.2.1 and shall be in accordance with table I,
subgroup 2 and table II herein.
* 4.4.2.1 Group B inspection, JAN and JANTX. Separate samples may be used for each step. In the event of a
lot failure, the resubmission requirements of MIL-PRF-19500 shall apply. In addition, all catastrophic failures
during conformance inspection shall be analyzed to the extent possible to identify root cause and corrective action.
Whenever a failure is identified as wafer lot and wafer processing related, the entire wafer lot and related devices
assembled from the wafer lot shall be rejected unless an appropriate determined corrective action to eliminate the
failures mode has been implemented and the devices from the wafer lot are screened to eliminate the failure
mode.
Step
Method
Condition
1
1026
Steady-state life: 1,000 hours minimum, VCB = 10 dc, power and ambient shall be
applied to achieve TJ = +150°C minimum using a minimum of PD = 75 percent of
maximum rated PT as defined in 1.3. n = 45 devices, c = 0. The sample size may be
increased and the test time decreased as long as the devices are stressed for a total of
45,000 device hours minimum, and the actual time of test is at least 340 hours.
Blocking life, TA = +150°C, VCB = 80 percent of rated voltage, 48 hours minimum.
2
1048
n = 45 devices, c = 0.
High-temperature life (non-operating), t = 340 hours, TA = +200°C. n = 22, c = 0.
3
1032
5
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