MIL-PRF-19500-366 Semiconductor Device, Transistor, Npn, Silicon, Amplifier, Types 2N3498, 2N3498L, 2N3498U4, 2N3499, 2N3499L, 2N3499U4, 2N3500, 2N3500L, N3500U4, 2N3501, 2N3501L, 2N3501Ub, And 2N3501U4, Jan, Jantx, Jantxv, Jans, Janhc, And Jankc, Jansm, Jansd, Jansp, Jansl, Jansr, Jansf, Jansg, Jansh, Janhcb, Janhcc, Jankcb, Jankcc, Jankccm, Jankccd, Jankccp, Jankccl, Jankccr, Jankccf, ...This specification covers the performance requirements for NPN, silicon, low-power amplifier and switching transistors. Four levels of product assurance are provided for each device type as specified in MIL-PRF-19500. Two levels of product assurance are provided for die. Radiation hardness assurance \(RHA\) level designators; "M", "D", "P", "L", "R", "F", "G", and "H" are appended to the device prefix to identify devices which have passed RHA requirements.

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MIL-PRF-19500/366P

4.3 Screening (JANS, JANTXV, and JANTX levels only). Screening shall be in accordance with table E-IV of

MIL-PRF-19500, and as specified herein. The following measurements shall be made in accordance with table I

herein. Devices that exceed the limits of table I herein shall not be acceptable.

Screen (see

Measurement

table E-IV of

MIL-PRF-19500)

JANS level

JANTX and JANTXV levels

(1) 3c

Thermal impedance method 3131 of

MIL-STD-750, see figures 11, 12, 13, and

MIL-STD-750, see figures 11, 12, 13, and 14,

14, and 4.3.3.

and 4.3.3.

ICBO2 and hFE4

Not applicable.

ICBO2 and hFE4

ICBO2 and hFE4; ĆICBO2 = 100 percent of

initial value or 5 nA dc, whichever is greater;

ĆhFE4 = �15 percent of initial value.

See 4.3.2.

Subgroups 2 and 3 of table I herein;

Subgroups 2 of table I herein;

ĆICBO2 = 100 percent of initial value

or 5 nA dc, whichever is greater;

ĆhFE4 = �15 percent of initial value.

(1) Shall be performed anytime after temperature cycling, screen 3a; JANTX and JANTXV levels do not need to

be repeated in screening requirements.

4.3.1 Screening (JANHC and JANKC). Screening of JANHC and JANKC die shall be in accordance with

MIL-PRF-19500, "Discrete Semiconductor Die/Chip Lot Acceptance". Burn-in duration for the JANKC level follows

JANS requirements; the JANHC follows JANTX requirements.

4.3.2 Power burn-in conditions. Power burn-in conditions are as follows: VCB = 10 - 30 V dc; power shall be

applied to achieve TJ = +135�C minimum using a minimum power dissipation = 75 percent of maximum rated PT (see

1.3). NOTE: No heat sink or forced air-cooling on the devices shall be permitted. With approval of the qualifying

activity and preparing activity, alternate burn-in criteria (hours, bias conditions, TJ, and mounting conditions) may be

used. A justification demonstrating equivalence is required. In addition, the manufacturing site s burn-in data and

performance history will be essential criteria for burn-in modification approval. Use method 3100 of MIL-STD-750 to

measure TJ.

* 4.3.3 Thermal impedance. The thermal impedance measurements shall be performed in accordance with

method 3131 of MIL-STD-750 using the guidelines in that method for determining IM, IH, tH, tMD (and VC where

appropriate). The thermal impedance limit shall comply with the thermal impedance graph in figures 11, 12, 13, and

14 (less than or equal to the curve value at the same tH time) and shall be less than the process determined statistical

maximum limit as outlined in method 3131 of MIL-STD-750. See table III group E, subgroup 4 herein.