MIL-PRF-19500-430 Semiconductor Device, Dual Field Effect Transistors, N-Channel, Silicon Types 2N5545, 2N5546, And 2N5547, Jan, Jantx, And JantxvThis specification covers the performance requirements for two electrically isolated, matched N-channel, junction, silicon field-effect transistors in one package. Three levels of product assurance are provided for each device type as specified in MIL-PRF-19500.

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MIL-PRF-19500/430C

3.3 Abbreviations, symbols, and definitions. Abbreviations, symbols, and definitions used herein shall be as specified in

|IDSS1|

--------- ........................................... Zero-gate-voltage drain current ratio.

|IDSS2|

|IG1 - IG2| ..................................... Gate current differential.

|VGS1 - VGS2| .............................. Gate-source voltage differential.

|Ć(VGS1 - VGS2)ĆTA| ................... Gate-source voltage differential change with temperature.

Vn ................................................. Equivalent short circuit input noise voltage for unity bandwidth.

|yfs|1

------

.......................................... Small-signal common-source forward transfer admittance ratio.

|yfs|2

||yos|1 - |yos|2| ............................. Small-signal common-source output admittance differential.

* 3.4 Interface and physical dimensions. The interface and physical dimensions shall be as specified in

3.4.1 Lead finish. Lead finish shall be solderable in accordance with MIL-PRF-19500. Where a choice of

lead finish is desired, it shall be specified in the acquisition document (see 6.2).

3.5 Marking. Marking shall be in accordance with MIL-PRF-19500.

3.6 Electrostatic discharge protection. The devices covered by this specification require electrostatic protection.

* 3.6.1 Handling. MOS devices must be handled with certain precautions to avoid damage due to the

accumulation of electrostatic charge. The following handling practices shall be followed:

Devices shall be handled on benches with conductive handling devices.

Ground test equipment, tools, and personnel handling devices.

Do not handle devices by the leads.

Store devices in conductive foam or carriers.

Avoid use of plastic, rubber, or silk in MOS areas.

Maintain relative humidity above 50 percent, if practical.

Care shall be exercised, during test and troubleshooting, to apply not more than maximum rated voltage to

any lead.

Gate must be terminated to source, R ≤ 100 kΩ, whenever bias voltage is to be applied drain to source.

3.7 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance

characteristics are as specified in 1.3, 1.4 and table I.

* 3.8 Electrical test requirements. The electrical test requirements shall be specified in table I herein.