MIL-PRF-19500-510 Semiconductor Device, Transistor, Npn, Silicon, Power, Type 2N6249, 2N6249T1, 2N6249T3, 2N6250, 2N6250T1, 2N6250T3, 2N6251, 2N6251T1, 2N6251T3, Jan, Jantx, Jantxv, Jans, Jansm, Jansd, Jansp, Jansl, Jansr, Jansf, Jansg, Jansh, Janhcb, Jankcb, Jankcbm, Jankcbd, Jankcbp, Jankcbl, Jankcbr, Jankcbf, Jankcbg, And JankcbhThis specification covers the performance requirements for NPN silicon, power transistors. Four levels of product assurance are provided for each device type as specified in MIL-PRF-19500. Two levels of product assurance are provided for each unencapsulated device type. Provisions for radiation hardness assurance \(RHA\) to eight radiation levels is provided for JANS and JANKC product assurance levels. RHA level designators "M", "D", "P", "L", "R", "F", "G", and "H" are appended to the device prefix to identify devices, which have passed RHA requirements.

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MIL-PRF-19500/510J

Temperature-Power Derating Curve

TC=25�C TO-257

140

120

100

125

150

175

200

225

Tc (�C) (Case)

DC Operation

Thermal Resistance Junction to Case = 1.3�C/W

Note: Max Finish-Alloy Temp = 175.0�C

NOTES:

1. Top curve is thermal runaway loci and cannot be used as a derate design curve since it exceeds the

maximum ratings for this part. Operating under this curve using these mounting conditions assures the

device will not have a thermal runaway. This is the true inverse of the worst case thermal resistance value

extrapolated out to the thermal runaway point.

2. Derate design curve constrained by the maximum junction temperature (TJ ≤ +200�C) and power rating

specified. (See 1.3 herein.)

3. Derate design curve chosen at TJ ≤ +150�C, where the maximum temperature of electrical test is

performed.

4. Derate design curves chosen at TJ ≤ +125�C, and +110�C to show power rating where most users want to

limit TJ in their application.

FIGURE 6. Derating for T3 (TO-257) packages.