INCH-POUND
The documentation and process conversion
measures necessary to comply with this revision
MIL-PRF-19500/545K
shall be completed by 29 November 2014.
29 August 2014
SUPERSEDING
MIL-PRF-19500/545J
6 February 2013
PERFORMANCE SPECIFICATION SHEET
*
SEMICONDUCTOR DEVICE, TRANSISTOR, PNP, SILICON, POWER,
TYPES 2N5151, 2N5153, 2N5151L, 2N5153L, 2N5151U3, AND 2N5153U3, JAN, JANTX, JANTXV, JANTXVF,
JANTXVR, JANS, JANHC, AND JANKC, JANSM, JANSD, JANSP, JANSL, JANSR, JANSF, JANSG,
JANSH, JANHCB, JANHCC, JANHCD, JANKCB, JANKCC, JANKCD, JANKCCM, JANKCCD, JANKCCP, JANKCCL,
JANKCCR, JANKCCF, JANKCCG, AND JANKCCH
This specification is approved for use by all Departments
and Agencies of the Department of Defense.
The requirements for acquiring the product described herein shall consist of
this specification sheet and MIL-PRF-19500.
1. SCOPE
1.1 Scope. This specification covers the performance requirements for PNP, silicon, power transistors for use in
high-speed power-switching applications. Four levels of product assurance are provided for each encapsulated
device type as specified in MIL-PRF-19500. Two levels of product assurance are provided for each unencapsulated
device type. RHA level designators "M", "D", "P", "L", "R", "F", "G", and "H" are appended to the device prefix to
identify devices, which have passed RHA requirements.
figure 5 (U3).
1.3 Maximum ratings. Unless otherwise specified, TC = +25°C.
*
Types
Reverse
VCEO
VEBO
IC
IC
PT
PT
TSTG and
VCBO
RθJA
RθJC
pulse
TA = +25°C
TC = +25°C
(3)
TJ
(2)
(2)
energy (4)
(1)
(1)
°C/W
°C/W
°C
W
W
V dc
V dc
V dc
A dc
A dc
mj
2N5151, L
1
10
175
10
-100
-80
-5.5
-2
-10
15
-65 to + 200
2N5153, L
1
10
175
10
-100
-80
-5.5
-2
-10
15
2N5151U3
1.16
100
150 (5)
1.75
-100
-80
-5.5
-2
-10
15
-65 to + 200
2N5153U3
1.16
100
150 (5)
1.75
-100
-80
-5.5
-2
-10
15
(1)
(2)
This value applies for Pw ≤ 8.3 ms, duty cycle ≤ 1 percent.
(3)
*
(4)
This rating is based on the capability of the transistors to operate safely in the unclamped inductive load
energy test circuit, see subgroup 5 of the group A inspection table and figure 13.
*
(5) Mounted on an FR4 printed circuit board.
Comments, suggestions, or questions on this document should be addressed to DLA Land and Maritime, ATTN:
VAC, P.O. Box 3990, Columbus, OH 43218-3990, or emailed to Semiconductor@dla.mil. Since contact
information can change, you may want to verify the currency of this address information using the ASSIST
Online database at https://assist.dla.mil.
AMSC N/A
FSC 5961
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