MIL-PRF-19500-558 Semiconductor Device, Unitized, Pnp, Silicon, Switching, Four Transistor Array, Types 2N6987, 2N6987U, And 2N6988, Jan, Jantx, Jantxv, Jans, Jansm, Jansd, Jansp, Jansl, Jansr, Jansf, Jansg, And JanshThis specification covers the performance requirements for PNP, silicon, switching transistors, four independent chip array. Four levels of product assurance are provided for each device type as specified in MIL-PRF-19500. Radiation hardness assurance \(RHA\) level designators "M", "D", "P", "L", "R", "F", "G", and "H" are appended to the device prefix to identify devices which have passed RHA requirements.

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MIL-PRF-19500/558J

4.5 Method of inspection. Methods of inspection shall be as specified in the appropriate tables and as follows.

4.5.1 Pulse measurements. Conditions for pulse measurement shall be as specified in section 4 of

MIL-STD-750.

4.5.2 Input capacitance. This test shall be conducted in accordance with method 3240 of MIL-STD-750, except

the output capacitor shall be omitted.

4.5.3 Independent transistor inspections. Inspections shall be performed on each transistor in the array.

4.5.4 Transistor-to-transistor resistance. The leads of each transistor shall be shorted together for this test. The

resistance shall be measured between each transistor in the array.

4.5.5 Delta requirements. Delta requirements shall be as specified below:

Step

Inspection

MIL-STD-750

Symbol

Limit

Method

Conditions

ĆICB02 (1)

Collector-base cutoff

3036

Bias condition D,

100 percent of initial

value or �8 nA dc,

VCB = 50 V dc

current

whichever is greater.

�25 percent change

ĆhFE4 (1)

Forward current transfer

3076

VCE = 10 V dc;

ratio

IC = 150 mA dc;

from initial reading.

pulsed see 4.5.1

(1) Devices which exceed the table I limits for this test shall not be accepted.