INCH-POUND
The documentation and process conversion measures
MIL-PRF-19500/368M
necessary to comply with this document shall be
2 October 2013
completed by 2 January 2014.
SUPERSEDING
MIL-PRF-19500/368L
20 November 2010
PERFORMANCE SPECIFICATION SHEET
SEMICONDUCTOR DEVICE, TRANSISTOR, NPN, SILICON, LOW-POWER
TYPES: 2N3439, 2N3439L, 2N3439UA, 2N3439U4, 2N3440, 2N3440L, 2N3440UA, AND
2N3440U4, JAN, JANTX, JANTXV, JANS, JANHCB, JANKCB, JANHCC, JANKCC JANSM,
JANSD, JANSP, JANSL, JANSR, JANSF, JANSG, JANSH, JANKCBM, JANKCBD,
JANKCBP, JANKCBL, JANKCBR, JANKCBF, JANKCBG, AND JANKCBH
This specification is approved for use by all Departments
and Agencies of the Department of Defense.
The requirements for acquiring the product described herein shall consist of
this specification sheet and MIL-PRF-19500.
1. SCOPE
1.1 Scope. This specification covers the performance requirements for NPN, silicon, low-power, high voltage
transistors. Four levels of product assurance are provided for each encapsulated device types as specified in
MIL-PRF-19500, and two levels of product assurance for each unencapsulated device type die. RHA level
designators "M", "D", "P", "L", "R", "F", "G", and "H" are appended to the device prefix to identify devices, which have
passed RHA requirements.
1.2 Physical dimensions. See figure 1 (similar to TO-5 and TO-39), figure 2 (JANHCB and JANKCB
(B versions)), figure 3 (2N3439UA and 2N3440UA surface mount versions), figure 4 (2N3439U4 and 2N3440U4
versions), and figure 5 (JANHCC and JANKCC (C versions)).
1.3 Maximum ratings. Unless otherwise specified, TA = +25°C.
Types
PT (1)
PT (2)
PT (2)
VCBO
VEBO
VCEO
IC
TSTG
RθJA
RθJC
RθJSP
and
(3)
(3)
(3)
TA =
TC =
TSP =
TJ
+25°C
+25°C
+25°C
°C/W
°C/W
°C/W
°C
W
W
W
V dc
V dc
V dc
A dc
2N3439
0.8
5.0
N/A
450
7
350
1.0
175
30
N/A
-65 to
2N3439L
0.8
5.0
N/A
450
7
350
1.0
175
30
N/A
+200
2N3439UA
0.8
N/A
2.0
450
7
350
1.0
175
N/A
70
2N3439U4
0.8
5
N/A
450
7
350
1.0
175
8
N/A
2N3440
0.8
5.0
N/A
175
30
N/A
300
7
250
1.0
2N3440L
0.8
5.0
N/A
175
30
N/A
300
7
250
1.0
2N3440UA
0.8
N/A
2.0
175
N/A
70
300
7
250
1.0
2N3440U4
0.8
5
N/A
175
8
N/A
300
7
250
1.0
(1) For derating, see figure 6.
(2) For derating, see figures 7, 8, and 9.
(3) For thermal impedance curves see figures 10, 11, 12, and 13.
* Comments, suggestions, or questions on this document should be addressed to DLA Land and Maritime,
ATTN: VAC, P.O. Box 3990, Columbus, OH 43218-3990, or emailed to Semiconductor@dla.mil. Since
contact information can change, you may want to verify the currency of this address information using the
ASSIST Online database at https://assist.dla.mil .
AMSC N/A
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