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MIL-PRF-19500-368 Semiconductor Device, Transistor, Npn, Silicon, Low-Power Types: 2N3439, 2N3439L, 2N3439Ua, 2N3439U4, 2N3440, 2N3440L, 2N3440Ua, And 2N3440U4, Jan, Jantx, Jantxv, Jans, Janhcb, Jankcb, Janhcc, Jankcc Jansm, Jansd, Jansp, Jansl, Jansr, Jansf, Jansg, Jansh, Jankcbm, Jankcbd, Jankcbp, Jankcbl, Jankcbr, Jankcbf, Jankcbg, And JankcbhThis specification covers the performance requirements for NPN, silicon, low-power, high voltage transistors. Four levels of product assurance are provided for each encapsulated device types as specified in MIL-PRF-19500, and two levels of product assurance for each unencapsulated device type die. RHA level designators "M", "D", "P", "L", "R", "F", "G", and "H" are appended to the device prefix to identify devices, which have passed RHA requirements.

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MIL-PRF-19500/368M

Dimensions

Symbol

Inches

Millimeters

Note

Min

Max

Min

Max

.215

.225

5.46

5.71

BL2

.225

5.71

.145

.155

3.68

3.93

BW2

.155

3.93

.061

.075

1.55

1.90

.003

0.08

.029

.042

0.74

1.07

LL1

.032

.048

0.81

1.22

LL2

.072

.088

1.83

2.23

.045

.055

1.14

1.39

.022

.028

0.56

0.71

LW2

.006

.022

0.15

0.56

Pin no.

Transistor

Collector

Emitter

Base

N/C

NOTES:

1. Dimensions are in inches.

2. Millimeters are given for general information only.

3. Dimension "CH" controls the overall package thickness. When a window lid is used, dimension "CH" must

increase by a minimum of .010 inch (0.254 mm) and a maximum of .040 inch (1.020 mm).

4. The corner shape (square, notch, radius, etc.) may vary at the manufacturer's option, from that shown on the

drawing.

* 5. Dimensions " LW2" minimum and "L3" minimum and the appropriate castellation length define an unobstructed

three-dimensional space traversing all of the ceramic layers in which a castellation was designed.

(Castellations are required on bottom two layers, optional on top ceramic layer.) Dimension " LW2" maximum

define the maximum width and depth of the castellation at any point on its surface.

Measurement of these dimensions may be made prior to solder dipping.

6. The coplanarity deviation of all terminal contact points, as defined by the device seating plane, shall not exceed

.006 inch (0.15mm) for solder dipped leadless chip carriers.

7. In accordance with ASME Y14.5M, diameters are equivalent to φx symbology.

* FIGURE 3. Physical dimensions, surface mount (2N3439UA, 2N3440UA) version.