MIL-PRF-19500-368 Semiconductor Device, Transistor, Npn, Silicon, Low-Power Types: 2N3439, 2N3439L, 2N3439Ua, 2N3439U4, 2N3440, 2N3440L, 2N3440Ua, And 2N3440U4, Jan, Jantx, Jantxv, Jans, Janhcb, Jankcb, Janhcc, Jankcc Jansm, Jansd, Jansp, Jansl, Jansr, Jansf, Jansg, Jansh, Jankcbm, Jankcbd, Jankcbp, Jankcbl, Jankcbr, Jankcbf, Jankcbg, And JankcbhThis specification covers the performance requirements for NPN, silicon, low-power, high voltage transistors. Four levels of product assurance are provided for each encapsulated device types as specified in MIL-PRF-19500, and two levels of product assurance for each unencapsulated device type die. RHA level designators "M", "D", "P", "L", "R", "F", "G", and "H" are appended to the device prefix to identify devices, which have passed RHA requirements.

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MIL-PRF-19500/368M

4.2.1 Group E qualification. Group E inspection shall be performed for qualification or re-qualification only. In

case qualification was awarded to a prior revision of the specification sheet that did not request the performance of

table III tests, the tests specified in table III herein that were not performed in the prior revision shall be performed on

the first inspection lot of this revision to maintain qualification.

* 4.3 Screening (JANS, JANTXV, and JANTX levels only). Screening shall be in accordance with MIL-PRF-19500

and as specified herein. The following measurements shall be made in accordance with table I herein. Devices that

exceed the limits of table I herein shall not be acceptable.

Screen

Measurement

(see table E-IV

of MIL-PRF-19500)

JANS level

JANTX and JANTXV levels

(1) 3c

Thermal impedance,

method 3131 of MIL-STD-750 (see 4.3.3)

Not applicable

ICBO1 and hFE1

48 hours minimum

ICBO1; hFE1; ĆICB01 = 100 percent of initial value

ICBO1 and hFE1

or 0.5 �A dc, whichever is greater;

ĆhFE1 = �15 percent of initial value.

See 4.3.2

Subgroups 2 and 3 of table I herein;

Subgroup 2 of table I herein;

ĆICB01 = 100 percent of initial value or

ĆICB01 = 100 percent of initial value or 200 nA dc,

200 nA dc, whichever is greater;

whichever is greater;

ĆhFE1 = �15 percent of initial value.

* (1) Thermal impedance, see 4.3.3. Shall be performed anytime after temperature cycling, screen 3a; TX and

TXV levels do not need to be repeated in screening requirements.

4.3.1 Screening (JANHC and JANKC). Screening of JANHC and JANKC die shall be in accordance with

MIL-PRF-19500. As a minimum, die shall be 100 percent probed to ensure the assembled chips will meet the

requirements of table I, subgroup 2.

4.3.2 Power burn-in conditions. Power burn-in conditions are as follows: VCB = 10 - 30 V dc. Power shall be

applied to achieve TJ = +135�C minimum using a minimum PD = 75 percent of PT maximum rated as defined in 1.3.

With approval of the qualifying activity and preparing activity, alternate burn-in criteria (hours, bias conditions, TJ, and

mounting conditions) may be used for JANTX and JANTXV quality levels. A justification demonstrating equivalence

is required. In addition, the manufacturing site's burn-in data and performance history will be essential criteria for

burn-in modification approval.

4.3.3 Thermal impedance. The thermal impedance measurements shall be performed in accordance with method

3131 of MIL-STD-750 using the guidelines in that method for determining IM, IH, tH, tMD (and VC where appropriate).

See table III, subgroup 4 and figures 10, 11, 12, and 13 herein.