INCH-POUND
The documentation and process conversion measures
necessary to comply with this document shall be
MIL-PRF-19500/396L
completed by 18 October 2013.
18 July 2013
SUPERSEDING
MIL-PRF-19500/396K
14 August 2007
PERFORMANCE SPECIFICATION SHEET
SEMICONDUCTOR DEVICE, TRANSISTOR, PNP, SILICON, SWITCHING,
TYPES 2N3762, 2N3762L, 2N3762U4, 2N3762UA, 2N3763, 2N3763L, 2N3763U4, 2N3763UA,
2N3764, AND 2N3765, JAN, JANTX, JANTXV, JANS, JANSM, JANSD, JANSP, JANSL, JANSR,
JANSF, JANSG, JANSH JANHCA, JANKCA, JANKCAM, JANKCAD, JANKCAP, JANKCAL,
JANKCAR, JANKCAF, JANKCAG, AND JANKCAH
This specification is approved for use by all Departments
and Agencies of the Department of Defense.
1. SCOPE
1.1 Scope. This specification covers the performance requirements for PNP silicon switching transistors. Four
levels of product assurance are provided for each encapsulated device type as specified in MIL-PRF-19500 and two
levels of product assurance are provided for each unencapsulated device type. RHA level designators "M", "D", "P",
"L", "R", "F', "G", and "H" are appended to the device prefix to identify devices, which have passed RHA
requirements.
1.2 Physical dimensions. See figure 1, ((2N3762L and 2N3763L (TO-5), 2N3762 and 2N3763 (TO-39)), figure 2
2N3764 and 2N3765 (TO-46), figure 3 (U4), figure 4 (UA), and figure 5 (die) herein.
1.3 Maximum ratings. Unless otherwise specified, TA = +25°C.
PT
PT
PT
PT
RθJC
RθJA
RθJA
RθJSP(
Types
TA =
TC =
TJ and
TSP(AM) =
TSP(IS) =
RθJC
RθJSP(IS)
Steel
Kovar
Steel
+25°C
+25°C
+25°C
+25°C
AM)
Kovar
(2)
TSTG
(2)
(2)
(2)
(2)
(1)
(1)
(1)
(1)
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C
W
W
W
W
2N3762, L
1.0
2
175
175
30
50
2N3762U4
10
15
2N3762UA
5
1.94
35
90
-65
2N3763, L
1.0
2
175
175
30
50
to
2N3763U4
10
15
+200
2N3763UA
5
1.94
35
90
2N3764
0.5
2
325
350
70
60
2N3765
0.5
2
325
350
70
60
Types
VCBO
VCEO
VEBO
IC
V dc
V dc
V dc
A dc
2N3762, L, 2N3762U4, 2N3762UA, 2N3764
40
40
5
1.5
2N3763, L, 2N3763U4, 2N3763UA, 2N3765
60
60
5
1.5
(1) For derating, see figures 6, 7, 8, 9, 10, 11, and 12.
(2) For thermal curves, see figures 13, 14, 15, 16, 17, 18, and 19.
* Comments, suggestions, or questions on this document should be addressed to DLA Land and Maritime, ATTN:
VAC, P.O. Box 3990, Columbus, OH 43218-3990, or emailed to Semiconductor@dla.mil . Since contact
information can change, you may want to verify the currency of this address information using the ASSIST Online
database at https://assist.dla.mil.
AMSC N/A
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