INCH-POUND
The documentation and process conversion measures
necessary to comply with this document shall be
MIL-PRF-19500/455K
completed by 16 September 2014.
16 June 2014
SUPERSEDING
MIL-PRF-19500/455J
29 June 2011
PERFORMANCE SPECIFICATION SHEET
SEMICONDUCTOR DEVICE, TRANSISTOR, NPN, SILICON, POWER SWITCHING,
TYPES 2N5664, 2N5665, 2N5666, 2N5666S, 2N5666U3, 2N5667, AND 2N5667S,
JAN, JANTX, JANTXV, JANTXVR, JANTXVF, JANS, JANSM, JANSD, JANSP, JANSL, JANSR, JANSF, JANSG,
JANSH, JANHC, AND JANKC, JANKCM, JANKCD, JANKCP, JANKCL, JANKCR, JANKCF, JANKCG, and JANKCH
This specification is approved for use by all Departments
and Agencies of the Department of Defense.
The requirements for acquiring the product described herein shall consist of
this specification sheet and MIL-PRF-19500.
1. SCOPE
1.1 Scope. This specification covers the performance requirements for NPN, silicon, power transistors for use in
high-speed power-switching applications. Four levels of product assurance are provided for each encapsulated
device type as specified in MIL-PRF-19500. Two levels of product assurance are provided for each un-encapsulated
device type as specified in MIL-PRF-19500. Provisions for radiation hardness assurance (RHA) to eight radiation
levels is provided for JANS product assurance level. Radiation hardness assurance (RHA) level designators; "M",
"D", "P", "L", "R", "F", "G", and "H" are appended to the device prefix to identify devices which have passed RHA
requirements.
* 1.2 Physical dimensions. See figure 1 (TO-66), figure 2 (TO-5 and TO-39), figure 3 (surface mount), figure 4
2N5664/2N5666).
1.3 Maximum ratings TA = +25°C unless otherwise specified.
Type
VCBO
VCEO
VEBO
IC
IB
PT1
PT2
RθJA
RθJC
Tstg and TJ
TA = +25°C TC = +100°C
(2)
(2)
(1)
(1)
°C/W (max) °C/W (max)
TC°C
W
W
V dc
V dc
V dc
A dc
A dc
2N5664
2.5
30
70
2.6
250
200
6
5
1
2.5
30
70
2.6
400
300
6
5
1
2N5665
1.2
15
145
6.7
250
200
6
5
1
-65 to +200
2N5666, S
1.5
35
116
2.3
250
200
6
5
1
2N5666U3
2N5667, S
1.2
15
145
6.7
400
300
6
5
1
* (1) For derating, see figures 7, 8, 9, 10, and 11.
* (2) For thermal impedance see figures 12, 13, 14, and 15.
Comments, suggestions, or questions on this document should be addressed to DLA Land and Maritime, ATTN:
VAC, P.O. Box 3990, Columbus, OH 43218-3990, or emailed to Semiconductor@dla.mil. Since contact
information can change, you may want to verify the currency of this address information using the ASSIST Online
database at https://assist.dla.mil .
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