MIL-PRF-19500-455 Semiconductor Device, Transistor, Npn, Silicon, Power Switching, Types 2N5664, 2N5665, 2N5666, 2N5666S, 2N5666U3, 2N5667, And 2N5667S, Jan, Jantx, Jantxv, Jantxvr, Jantxvf, Jans, Jansm, Jansd, Jansp, Jansl, Jansr, Jansf, Jansg, Jansh, Janhc, And Jankc, Jankcm, Jankcd, Jankcp, Jankcl, Jankcr, Jankcf, Jankcg, And JankchThis specification covers the performance requirements for NPN, silicon, power transistors for use in high-speed power-switching applications. Four levels of product assurance are provided for each encapsulated device type as specified in MIL-PRF-19500. Two levels of product assurance are provided for each un-encapsulated device type as specified in MIL-PRF-19500. Provisions for radiation hardness assurance \(RHA\) to eight radiation levels is provided for JANS product assurance level. Radiation hardness assurance \(RHA\) level designators; "M", "D", "P", "L", "R", "F", "G", and "H" are appended to the device prefix to identify devices which have passed RHA requirements.

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MIL-PRF-19500/455K

4.3 Screening (list applicable JAN levels). Screening shall be in accordance with table E-IV of MIL-PRF-19500

and as specified herein. The following measurements shall be made in accordance with table I herein. Devices that

exceed the limits of table I herein shall not be acceptable.

Screen (see table E-IV

Measurement

of MIL-PRF-19500)

JANS level

JANTX and JANTXV levels

(1) 3c

Thermal impedance method 3131 of

MIL-STD-750, see 4.3.3.

MIL-STD-750, see 4.3.3. (2)

ICES1 and hFE2

ICES1

ICES1 and hFE2;

ĆICES1 = 100 percent of initial value or

ĆICES1 = 100 percent of initial value

10 nA dc, whichever is greater;

or 20 nA dc, whichever is greater.

ĆhFE2 = �15 percent.

See 4.3.1.

Subgroups 2 and 3 of table I herein;

Subgroup 2 of table I herein;

ĆICES1 = +100 percent of initial value or

ĆICES1 = +100 percent of initial value

10 nA dc, whichever is greater.

or 20 nA dc, whichever is greater.

ĆhFE2 = �15 percent.

ĆhFE2 = �25 percent.

(1) Thermal impedance limits shall not exceed figures 12, 13, 14, and 15.

(2) Shall be performed anytime after temperature cycling, screen 3a; JANTX and JANTXV levels do not

need to be repeated in screening requirements.

4.3.1 Power burn-in conditions. Power burn-in conditions are as follows: TJ = +187.5 �12.5�C, VCE = 100 V dc,

applied PT minimum of PT1 = 75 percent, TA ≤ +55�C. Burn-in duration for lot acceptance for the JANKC level follows

JANS requirements. Burn-in duration for lot acceptance for the JANHC level follows JANTX requirements.

4.3.2 Screening (JANHC and JANKC). Screening of JANHC and JANKC die shall be in accordance with

MIL-PRF-19500. As a minimum, die shall be 100 percent probed to insure the assembled chips will meet the

requirements of table I, subgroup 2.

4.3.3 Thermal impedance. The thermal impedance measurements shall be performed in accordance with method

3131 of MIL-STD-750 using the guidelines in that method for determining IM, IH, tH, (and VC where appropriate).

Measurement delay time (tMD) = 70 �S maximum. The thermal impedance limit used in screen 3c of 4.3 and the

subgroup 2 of table I herein shall comply with the thermal impedance graph on figures 10, 11, 12, and 13 (less than

or equal to the curve value at the same tH time) and shall be less than the process determined statistical maximum

limit as outlined in method 3131. See table III, group E, subgroup 4 herein.

4.4 Conformance inspection. Conformance inspection shall be in accordance with MIL-PRF-19500 and as

specified herein. If alternate screening is being performed in accordance with E.5.3.1d of MIL-PRF-19500 a sample

of screened devices shall be submitted to and pass the requirements of group A1 and A2 inspection only (table VIb,

group B, subgroup 1 is not required to be performed again if group B has already been satisfied in accordance with

4.4.2).