MIL-PRF-19500-603 Semiconductor Device, Field Effect Radiation Hardened \(Total Dose Only\) Transistors, N-Channel, Silicon, Types 2N7268, 2N7269, 2N7270, 2N7394, 2N7268U, 2N7269U, 2N7270U, And 2N7394U, Jantxvr, F, G, H; Jansr, F, G, And HThis specification covers the performance requirements for an N-channel, enhancement-mode, MOSFET, radiation hardened \(total dose only\), power. Two levels of product assurance are provided for each device type specified in MIL-PRF-19500, with avalanche energy maximum rating \(EAS\) and maximum avalanche current \(IAS\). See 6.5 for JANHC and JANKC die versions.

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MIL-PRF-19500/603J

3. REQUIREMENTS

3.1 General. The individual item requirements shall be as specified in MIL-PRF-19500 and as modified herein.

3.2 Qualification. Devices furnished under this specification shall be products that are manufactured by a

manufacturer authorized by the qualifying activity for listing on the applicable qualified manufacturer's list (QML)

before contract award (see 4.2 and 6.3).

3.3 Abbreviations, symbols, and definitions. Abbreviations, symbols, and definitions used herein shall be as

specified in MIL-PRF-19500 and as follows.

IAS ........ Rated avalanche current, nonrepetitive

nC ........ nano Coulomb.

3.4 Interface and physical dimensions. The interface and physical dimensions shall be as specified in

MIL-PRF-19500 and on figure 1 and 2 herein. Methods used for electrical isolation of the terminal feedthroughs shall

employ materials that contain a minimum of 90 percent AL2O3 (ceramic). Examples of such construction techniques

are metallized ceramic eyelets or ceramic walled packages.

3.4.1 Lead finish. Lead finish shall be solderable in accordance with MIL-PRF-19500, MIL-STD-750, and herein.

Where a choice of lead finish is desired, it shall be specified in the acquisition document (see 6.2).

3.4.2 Internal construction. Multiple chip construction is not permitted.

3.5 Marking. Marking shall be in accordance with MIL-PRF-19500.

3.6 Electrostatic discharge protection. The devices covered by this specification require electrostatic discharge

protection.

3.6.1 Handling. MOS devices must be handled with certain precautions to avoid damage due to the accumulation

of static charge. However, the following handling practices are recommended (see 3.6).

Devices should be handled on benches with conductive handling devices.

Ground test equipment, tools, and personnel handling devices.

Do not handle devices by the leads.

Store devices in conductive foam or carriers.

Avoid use of plastic, rubber, or silk in MOS areas.

Maintain relative humidity above 50 percent if practical.

Care should be exercised during test and troubleshooting to apply not more than maximum rated voltage to

any lead.

Gate must be terminated to source, R ≤ 100 kΩ, whenever bias voltage is to be applied drain to source.

3.7 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance

characteristics are as specified in 1.3, 1.4, and table I herein.

3.8 Electrical test requirements. The electrical test requirements shall be as specified in table I.

3.9 Workmanship. Semiconductor devices shall be processed in such a manner as to be uniform in quality and

shall be free from other defects that will affect life, serviceability, or appearance.