The documentation and process conversion
INCH-POUND
measures necessary to comply with this document
MIL-PRF-19500/421G
shall be completed by 14 May 2004.
14 March 2004
SUPERSEDING
MIL-PRF-19500/421F
25 August 2001
* PERFORMANCE SPECIFICATION SHEET
SEMICONDUCTOR DEVICE, DUAL TRANSISTOR, UNITIZED, NPN/PNP,
COMPLEMENTARY, SILICON, TYPES 2N3838, 2N4854, AND 2N4854U,
JAN, JANTX, AND JANTXV
This specification is approved for use by all Departments
and Agencies the Department of Defense.
*
The requirements for acquiring the product described herein shall consist of
this specification sheet and MIL-PRF-19500.
1. SCOPE
1.1 Scope. This specification covers the performance requirements for unitized, dual transistors which contain a
pair of electrically isolated complementary NPN and PNP silicon triode transistors in one package. Three levels of
product assurance are provided for each device type as specified in MIL-PRF-19500.
1.2 Polarity designation. Voltages and currents of limits and test conditions shown herein apply to the NPN
transistor. For the PNP transistor, the values are the same, but the polarity designations are the opposite.
1.3 Physical dimensions. See figures 1 (6 lead flatpak), 2 (similar to TO-78), and 3 (surface mount).
* 1.4 Maximum ratings.
PT at TA = +25°C
PT at TC = +25°C (1)
Types
TJ and TSTG
RθJA
RθJA
RθJC
RθJC
One
Total
One
Total
One
Total
One
Total
transistor
device
transistor
device
transistor
device
transistor
device
°C/W
°C
°C/W
°C/W
°C/W
W
W
W
W
0.25
0.35
0.7
1.4
2N3838
700
500
250
125
-65 to +200
0.30
0.60
1.0
2.0
2N4854
584
292
175
87
0.30
0.60
1.0
2.0
2N4854U
584
292
175
87
Types
Lead to case
V1C-2C
IC
TJ
VCBO
VEBO
VCEO
voltage
°C
V dc
mA dc
V dc
V dc
V dc
V dc
±120
±120
600
60
5
40
2N3838
200
±120
±120
600
60
5
40
2N4854, 2N4854U
200
(1) TC rating does not apply to surface mount devices (2N4854U).
(2) For TA > +25°C, derate linearly 1.43 mW/°C one transistor, 2.00 mW/°C both transistors.
(3) For TA > +25°C, derate linearly 1.71 mW/°C one transistor, 3.43 mW/°C both transistors.
(4) For TC > +25°C, derate linearly 4.0 mW/°C one transistor, 8.0 mW/°C both transistors.
(5) For TC > +25°C, derate linearly 5.71 mW/°C one transistor, 11.43 mW/°C both transistors.
* Comments, suggestions, or questions on this document should be addressed to Defense Supply Center,
Columbus, ATTN: DSCC-VAC, P.O. Box 3990, Columbus, OH 43216-5000, or emailed to
Semiconductor@dscc.dla.mil . Since contact information can change, you may want to verify the currency of this
address information using the ASSIST Online database at https://www.dodssp.daps.mil/.
AMSC N/A
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