MIL-PRF-19500/562E
3. REQUIREMENTS
3.1 General. The individual item requirements shall be as specified in MIL-PRF-19500 and as modified herein.
3.2 Qualification. Devices furnished under this specification shall be products that are manufactured by a
manufacturer authorized by the qualifying activity for listing on the applicable qualified manufacturer's list (QML)
before contract award (see 4.2 and 6.3).
3.3 Abbreviations, symbols, and definitions. Abbreviations, symbols, and definitions used herein shall be as
specified in MIL-PRF-19500 and as follows.
nC - - - - - - - - - - - - - - - - - - - - -
nano Coulomb.
3.4 Interface and physical dimensions. The interface and physical dimensions shall be as specified in
MIL-PRF-19500 and on figure 1 (TO-204AA), 2, 3, and 4 (JANHC and JANKC) herein.
3.4.1 Lead finish. Lead finish shall be solderable in accordance with MIL-PRF-19500, MIL-STD-750 and herein.
Where a choice of lead finish is desired, it shall be specified in the acquisition document (see 6.2).
3.4.2 Internal construction. Multiple chip construction shall not be permitted.
3.5 Marking. Devices shall be marked in accordance with MIL-PRF-19500.
3.6 Electrical performance characteristics. Unless otherwise specified, the electrical performance characteristics
are as specified in 1.3, 1.4, and table I herein.
3.7 Electrostatic discharge protection. The devices covered by this specification require electrostatic protection.
3.7.1 Handling. MOS devices must be handled with certain precautions to avoid damage due to the accumulation
of static charge. The following handling practices shall be followed:
a.
Devices shall be handled on benches with conductive handling devices.
b.
Ground test equipment, tools, and personnel handling devices.
c.
Do not handle devices by the leads.
d.
Store devices in conductive foam or carriers.
e.
Avoid use of plastic, rubber, or silk in MOS areas.
f.
Maintain relative humidity above 50 percent if practical.
g.
Care shall be exercised, during test and troubleshooting, to apply not more than maximum rated voltage to
any lead.
Gate must be terminated to source, R ≤ 100 kΩ, whenever bias voltage is to be applied drain to source.
h.
3.8 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table I.
3.9 Workmanship. Semiconductor devices shall be processed in such a manner as to be uniform in quality and
shall be free from other defects that will affect life, serviceability, or appearance.
7
For Parts Inquires call Parts Hangar, Inc (727) 493-0744
© Copyright 2015 Integrated Publishing, Inc.
A Service Disabled Veteran Owned Small Business