MIL-PRF-19500-615 Semiconductor Device, Filed Effect Radiation Hardened Transistors, P-Channel, Silicon, Types 2N7382 And 2N7383, Jantxv M, D, R, And F And Jans M, D, R, And FThis specification covers the performance requirements for a P-channel, radiation hardened, enhancement mode, MOSFET, power transistor intended for use in high density power switching applications. Two levels of product assurance are provided for each device type as specified in MIL-PRF-19500, with avalanche energy ratings \(EAS\) and maximum avalanche current \(IAS\). See 6.5 for JANHC and JANKC die versions.

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MIL-PRF-19500/615G

3. REQUIREMENTS

3.1 General. The individual item requirements shall be as specified in MIL-PRF-19500 and as modified herein.

3.2 Qualification. Devices furnished under this specification shall be products that are manufactured by a

manufacturer authorized by the qualifying activity for listing on the applicable qualified manufacturer's list (QML)

before contract award (see 4.2 and 6.3).

3.3 Abbreviations, symbols, and definitions. Abbreviations, symbols, and definitions used herein shall be as

3.4 Interface and physical dimensions. Interface and physical dimensions shall be as specified in

MIL-PRF-19500 and on figure 1 herein. Methods used for electrical isolation of the terminal feedthroughs shall

employ materials that contain a minimum of 90 percent AL2O3 (ceramic). Examples of such construction techniques

are metallized ceramic eyelets or ceramic walled packages.

3.4.1 Lead material and finish. Lead material shall be Kovar, Alloy 52, and a copper core is permitted. Lead

finish shall be solderable in accordance with MIL-PRF-19500, MIL-STD-750, and herein. Where a choice of lead

finish is desired, it shall be specified in the acquisition requirement (see 6.2).

3.4.2 Internal construction. Multiple chip construction is not permitted to meet the requirements of this

specification.

3.5 Marking. Marking shall be in accordance with MIL-PRF-19500.

3.6 Electrostatic discharge protection. The devices covered by this specification require electrostatic protection.

3.6.1 Handling. MOS devices must be handled with certain precautions to avoid damage due to the

accumulation of electrostatic charge. The following handling practices shall be followed:

Devices shall be handled on benches with conductive handling devices.

Ground test equipment, tools, and personnel handling devices.

Do not handle devices by the leads.

Store devices in conductive foam or carriers.

Avoid use of plastic, rubber, or silk in MOS areas.

Maintain relative humidity above 50 percent if practical.

Care shall be exercised, during test and troubleshooting, to apply not more than maximum rated voltage to

any lead.

Gate must be terminated to source, R ≤ 100 kΩ, whenever bias voltage is to be applied drain to source.

3.7 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance

characteristics are as specified in 1.3, 1.4, and table I herein.

3.8 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table I

herein.

3.9 Workmanship. Semiconductor devices shall be processed in such a manner as to be uniform in quality and

shall be free from other defects that will affect life, serviceability, or appearance.