MIL-PRF-19500/357M
4.4 Conformance inspection. Conformance inspection shall be in accordance with MIL-PRF-19500 and as
specified herein. If alternate screening is being performed in accordance with MIL-PRF-19500, a sample of screened
devices shall be submitted to and pass the requirements of table I, group A, subgroup 1, subgroup 2 inspection only.
4.4.1 Group A inspection. Group A inspection shall be conducted in accordance with table E-V of
MIL-PRF-19500 and table I herein.
4.4.2 Group B inspection. Group B inspection shall be conducted in accordance with the conditions specified for
subgroup testing in table E-VIa (JANS) of MIL-PRF-19500 and 4.4.2.1 herein. Electrical measurements (end-points)
and delta requirements shall be in accordance with table I, group A, subgroup 2 and 4.5.4 herein. See 4.4.2.2 for
JAN, JANTX, and JANTXV group B testing. Electrical measurements (end-points) and delta requirements for JAN,
JANTX, and JANTXV shall be after each step in 4.4.2.2 and shall be in accordance with table I, group A, subgroup 2
and 4.5.4 herein.
4.4.2.1 Group B inspection, table E-VIa (JANS) of MIL-PRF-19500.
Subgroup
Method
Condition
VCB = 10 - 30 V dc; 2,000 cycles. No heat sink or forced-air cooling on devices shall be
B4
1037
permitted.
B5
1027
occurs, resubmission shall be at the test conditions of the original sample.)
Option 1: 96 hours minimum, sample size in accordance with table E-VIa of
MIL-PRF-19500 adjust TA or PD to achieve TJ = +275°C minimum.
Option 2: 216 hours minimum, sample size = 45, c = 0; adjust TA or PD to achieve
TJ = +225°C minimum.
4.4.2.2 Group B inspection, table E-VIb (JAN, JANTX, and JANTXV) of MIL-PRF-19500. Separate samples may
be used for each step. In the event of a lot failure, the resubmission requirements of MIL-PRF-19500 shall apply. In
addition, all catastrophic failures during CI shall be analyzed to the extent possible to identify root cause and
corrective action. Whenever a failure is identified as wafer lot and /or wafer processing related, the entire wafer lot
and related devices assembled from the wafer lot shall be rejected unless an appropriate determined corrective
action to eliminate the failures mode has been implemented and the devices from the wafer lot are screened to
eliminate the failure mode.
Step
Method
Condition
1
1026
Steady-state life: 1,000 hours minimum, VCB = 10 V dc, power shall be applied to achieve
TJ = +150°C minimum using a minimum of PD = 75 percent of maximum rated PT as
defined in 1.3. n = 45 devices, c = 0. The sample size may be increased and the test time
decreased as long as the devices are stressed for a total of 45,000 device hours minimum,
and the actual time of test is at least 340 hours.
Blocking life, TA = +150°C, VCB = 80 percent of rated voltage, 48 hours minimum.
2
1048
n = 45 devices, c = 0.
High-temperature life (non-operating), t = 340 hours, TA = +200°C. n = 22, c = 0.
3
1032
10
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