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MIL-PRF-19500-597 Semiconductor Device, Transistors, Quad, Field Effect, N-Channel, Silicon, Type 2N7334, Jan, Jantx, Jantxv, Jans, Janhc, And JankcThis specification covers the performance requirements for quad N-channel, enhancement-mode, MOSFET, power transistor with avalanche energy ratings \(EAS and EAR\) and maximum avalanche current \(IAR\). Four levels of product assurance are provided for each hermetic encapsulated device type as specified in MIL?√PRF?√19500. Two levels of product assurance are provided for each unencapsulated device type \(die\) as specified in MIL?√PRF?√19500.

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MIL­PRF­19500/597G
TABLE I. Group A inspection.
Limit
Inspection 1/
Unit
Symbol
Max
Min
Method
Conditions
Subgroup 1
Visual and mechanical
2071
inspection
Subgroup 2
Thermal impedance 2/
3161
ZθJC
V(BR)DSS
Breakdown voltage,
3407
Bias condition C
100
V dc
VGS = 0 V dc, ID = 1 mA dc,
drain-to-source
VDS ≥ VGS,
VGS(th)1
Gate-to-source
3403
2.0
4.0
V dc
ID = 0.25 mA dc
voltage (threshold)
Bias condition C, VGS = +20 V dc,
IGSSF1
Gate current (forward)
3411
+100
nA dc
VDS = 0
Bias condition C, VGS = ­20 V dc,
IGSSR1
Gate current (reverse)
3411
­100
nA dc
VDS = 0
µA dc
Bias condition C, VGS = 0 V dc,
IDSS1
Drain current
3413
25
VDS = 80 percent of rated VDS
Ω
Bias condition A, VGS = 10 V dc,
rDS(on)1
Static drain-to-source
3421
0.70
ID = rated ID2 (see 1.3),
on-state resistance
pulsed (see 4.5.1)
Ω
ID = ID1 (see 1.3)
rDS(on)2
0.80
VGS = 0 V, ID = ID1,
VSD
Forward voltage
4011
1.5
V
pulsed (see 4.5.1)
Subgroup 3
TC = TJ = +125°C
High temperature operation:
IGSS2
Gate current
3411
Bias condition C,
±200
nA dc
VGS = +20 V dc and ­20 V dc,
VDS = 0 V dc
Bias condition C, VGS = 0 V dc,
IDSS2
Drain current
3413
0.25
mA dc
VDS = 80 percent of rated VDS
Ω
Bias condition A, VGS = 10 V dc,
rDS(on)3
Static drain-to-source
3421
1.4
ID = rated ID2, pulsed (see 4.5.1),
on-state resistance
See footnotes at end table.
11



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