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MIL-PRF-19500-597 Semiconductor Device, Transistors, Quad, Field Effect, N-Channel, Silicon, Type 2N7334, Jan, Jantx, Jantxv, Jans, Janhc, And JankcThis specification covers the performance requirements for quad N-channel, enhancement-mode, MOSFET, power transistor with avalanche energy ratings \(EAS and EAR\) and maximum avalanche current \(IAR\). Four levels of product assurance are provided for each hermetic encapsulated device type as specified in MIL?√PRF?√19500. Two levels of product assurance are provided for each unencapsulated device type \(die\) as specified in MIL?√PRF?√19500.

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MIL­PRF­19500/597G
3. REQUIREMENTS
3.1 General. The individual item requirements shall be as specified in MIL­PRF­19500 and as modified herein.
3.2 Qualification. Devices furnished under this specification shall be products that are manufactured by a
manufacturer authorized by the qualifying activity for listing on the applicable qualified manufacturer's list (QML)
before contract award (see 4.2 and 6.3).
3.3 Abbreviations, symbols, and definitions. Abbreviations, symbols, and definitions used herein shall be as
specified in MIL­PRF­19500.
Rated avalanche current, nonrepetitive.
IAS
nC
nano coulomb.
3.4 Interface and physical dimensions. The interface requirements and physical dimensions shall be as specified
in MIL­PRF­19500 and on figure 1 (MO-036AB) and figures 2 and 3 (unencapsulated die) herein.
3.4.1 Lead finish. Unless otherwise specified, the lead finish shall be solderable as defined in MIL­STD­750,
MIL­PRF­19500, and herein. Where a choice of lead finish is desired, it shall be specified in the acquisition
document (see 6.2).
3.4.2 Pin out. The pin out of the device types shall be as shown on figures 1, 2, and 3.
3.5 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance
characteristics are as specified in 1.3, 1.4, and table I herein.
3.5.1 Electrostatic discharge protection. The devices covered by this specification require electrostatic protection.
3.5.2 Handling. MOS devices must be handled with certain precautions to avoid damage due to the accumulation
of electrostatic charge. The following handling practices shall be followed:
a.
Devices shall be handled on benches with conductive handling devices.
b.
Ground test equipment, tools, and personnel handling devices.
c.
Do not handle devices by the leads.
d.
Store devices in conductive foam or carriers.
e.
Avoid use of plastic, rubber, or silk in MOS areas.
f.
Maintain relative humidity above 50 percent if practical.
g.
Care shall be exercised, during test and troubleshooting, to apply not more than maximum rated voltage to
any lead.
Gate must be terminated to source, R ≤ 100 kΩ, whenever bias voltage is to be applied drain to source.
h.
3.6 Electrical test requirements. The electrical test requirements shall be as specified in table I.
3.7 Marking. Marking shall be in accordance with MIL­PRF­19500.
3.8 Workmanship. Semiconductor devices shall be processed in such a manner as to be uniform in quality and
shall be free from other defects that will affect life, serviceability, or appearance.
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