MIL-PRF-19500/605D
3. REQUIREMENTS
3.1 General. The individual item requirements shall be as specified in MIL-PRF-19500 and as modified herein.
3.2 Qualification. Devices furnished under this specification shall be products that are manufactured by a
manufacturer authorized by the qualifying activity for listing on the applicable qualified manufacturer's list (QML)
before contract award (see 4.2 and 6.3).
3.3 Abbreviations, symbols, and definitions. Abbreviations, symbols, and definitions used herein shall be as
specified in MIL-PRF-19500 and as follows: IAS - Rated avalanche current, non-repetitive.
3.4 Interface and physical dimensions. The interface and physical dimensions shall be as specified in
MIL-PRF-19500, and figure 1 (TO-254AA) herein.
3.4.1 Lead material and finish. Lead material shall be Kovar or Alloy 52; a copper core or plated core is permitted.
Lead finish shall be solderable as defined in MIL-PRF-19500, MIL-STD-750, and herein. Where a choice of lead
finish is desired, it shall be specified in the acquisition documents (see 6.2).
3.4.2 Internal construction. Multiple chip construction is not permitted to meet the requirements of this
specification.
3.5 Marking. Marking shall be in accordance with MIL-PRF-19500. At the option of the manufacturer, marking of
the country of origin may be omitted from the body of the transistor, but shall be retained on the initial container.
3.6 Electrostatic discharge protection. The devices covered by this specification require electrostatic discharge
protection.
3.6.1 Handling. MOS devices must be handled with certain precautions to avoid damage due to the accumulation
of static charge. However, the following handling practices are recommended (see 3.6).
a.
Devices should be handled on benches with conductive handling devices.
b.
Ground test equipment, tools, and personnel handling devices.
c.
Do not handle devices by the leads.
d.
Store devices in conductive foam or carriers.
e.
Avoid use of plastic, rubber, or silk in MOS areas.
f.
Maintain relative humidity above 50 percent if practical.
g.
Care should be exercised during test and troubleshooting to apply not more than maximum rated voltage to
any lead.
Gate must be terminated to source, R ≤ 100 kΩ, whenever bias voltage is to be applied drain to source.
h.
3.7 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance
characteristics are as specified in 1.3, 1.4, and table I.
3.8 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table I.
3.9 Workmanship. Semiconductor devices shall be processed in such a manner as to be uniform in quality and
shall be free from other defects that will affect life, serviceability, or appearance.
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